Giới thiệu
Tsung-Yi Ho là Giáo sư tại Khoa Khoa học và Kỹ thuật Máy tính, Đại học Trung văn Hồng Kông (CUHK). Ông nhận bằng Tiến sĩ Kỹ thuật Điện tại Đại học Quốc gia Đài Loan năm 2005. Hướng nghiên cứu của ông tập trung vào tự động hóa thiết kế và các công nghệ điện toán tiên tiến, đặc biệt là tự động hóa thiết kế cho vi chip vi lưu sinh học.
Ông từng nhận nhiều học bổng và danh hiệu quốc tế uy tín, bao gồm JSPS Invitational Fellowship, Humboldt Research Fellowship, Hans Fischer Fellowship và International Visiting Research Scholarship. Ông cũng là tác giả của các công trình đạt Giải Bài báo Xuất sắc tại VLSI Test Symposium năm 2013 và IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems năm 2015.
Ông đã đảm nhiệm nhiều vị trí lãnh đạo trong ACM và IEEE, trong đó hiện là President-Elect của IEEE Council on Electronic Design Automation (CEDA) và thành viên Ban Điều hành ASP-DAC và ICCAD. Ông là Distinguished Member của ACM và Fellow của IEEE.
· Trí tuệ nhân tạo và Học máy
· Tự động hóa thiết kế điện tử
· Thiết kế vi chip vi lưu
· Điện toán lượng tử
· Tự động hóa thiết kế điện tử
· Tối ưu hóa rời rạc
· Lý thuyết tính toá
1. X. Huang, J. Wang, Z. Yu, B. Guo, H. Ma, T.-Y. Ho, U. Schlichtmann, and K. Chakrabarty, “Path-Driven Washing and Drying Co-Optimization in Continuous-Flow Lab-on-Chips,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), Vol. 45 Issue 1, pp. 148-161, January 2026.
2. B. Liu, C. Jiang, Q. Xu, H. Yao, T.-Y. Ho, and B. Yuan, “Efficient Routing-based Synthesis for Digital Microfluidic Biochips via Reinforcement Learning,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), Vol. 45 Issue 1, pp. 162-175, January 2026.
3. S. Li, Z. Zhuang, K. Yao, M. Liu, W. Sheng, B. Yu, and T.-Y. Ho, “HiePlace: Efficient Hierarchical PCB Placement,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), Vol. 45 Issue 1, pp. 428-440, January 2026.
4. L. Xiao, S. Lin, J. Liu,Q. Duan, T.-Y. Ho, and F. Y. Young, “InstantGR: Scalable GPU Parallelization for 3-D Global Routing,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), Vol. 45 Issue 1, pp. 441-452, January 2026.
5. S. Liang, Z. Zhuang, K.-Y. Chao, B. Yu, and T.-Y. Ho, “Multi-Layer Package Power/Ground Planes Synthesis with Balanced DC IR Drops: A Game-Theoretic Optimization Approach,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), Vol. 45 Issue 1, pp. 453-465, January 2026.
6. W. Ma, X. Yang, S. Zeng, T. Liu, L. Shen, H. Wang, S. Li, K. Hong, Z. Zhu, X. Ning, T.-Y. Ho, G. Dai and Y. Wang, “CD-LLM: A Heterogeneous Multi-FPGA System for Batched Decoding of 70B+ LLMs using a Compute-Dedicated Architecture,” ACM Transactions on Reconfigurable Technology and Systems (ACM TRET), Vol. 19 Issue 1, No. 8, January 2026.
7. R. Fu, M. Zhou, S. Chen, X. Chen, J. Huang, X. Ye, D. Fan, Z. Zhang, and T.-Y. Ho, “JPnR: A Length-Matching Placement and Routing Framework for Single-Flux-Quantum Circuits,” IEEE Transactions on Computers (IEEE TC), vol. 75 Issue 1, 2026 (Featured Paper).
8. S. Qi, Z. Yu, B. Guo, S. Li, Z. Li, H. Ma, T.-Y. Ho, K. Chakrabarty, and X. Huang, “Design Automation Techniques for Microfluidic Fully Programmable Valve Array Biochips: A Systematic Survey,” ACM Transactions on Design Automation of Electronic Systems (ACM TODAES), Vol. 31 Issue 1, No. 1, January 2026.
9. H. Cai, G. Liu, W. Guo, Z. Li, T.-Y. Ho, and X. Huang, “Adaptive Control-Logic Routing with Length Matching and Fault Tolerance for FPVA Biochips Using Deep Reinforcement Learning,” ACM Transactions on Design Automation of Electronic Systems (ACM TODAES), Vol. 31 Issue 1, No. 3, January 2026.
10. Z. Zhuang, W.-S. Hung, MD. Kabir, Y. Peng, and T.-Y. Ho, “Adaptive Redistribution Layer Routing for Chiplet-Package Co-Design in 2.5D System,” ACM Transactions on Design Automation of Electronic Systems (ACM TODAES), Vol. 31 Issue 3, No. 47, May 2026.
11. W.-L. Lee, D.-L. Lin, S. Jiang, C.-H. Chiu, Y. Lin, B. Yu, T.-Y. Ho, and T.-W. Huang, “G-kway: Multilevel GPU-Accelerated 𝑘-way Graph Partitioner using Task Graph Parallelism,” ACM Transactions on Design Automation of Electronic Systems (ACM TODAES), Vol. 31 Issue 3, No. 52, May 2026.
12. H. Liu, S. Liu, Z. Qi, T.-Y. Ho, and Bei Yu, “Selecting Nets to Rip Up and Reroute via SAT,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD, Vol. 45 Issue 5, pp. 2136-2140, May 2026.
13. A. Sarma, S. Jiang, W. Lee, T.-Y. Ho, and T.-W. Huang, “TIMBER: A Fast Algorithm for Timing and Power Optimization using Multi-bit Flip-flops,” Proceedings of IEEE/ACM Asia and South Pacific
Design Automation Conference (ASPDAC), pp., Hong Kong, January 2026.
14. R. Fu, L. Shen, Z. Wang, Z. Lei, Z. Wang, J. Huang, B. Yu, and T.-Y. Ho, “DCLOG: Don’t Cares-based Logic Optimization using Pre-training Graph Neural Networks,” Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), pp., Hong Kong, January 2026.
15. S. Ren, Z. Zhuang, R. Fu, L. Jin, L. Shen, B. Yu, and T.-Y. Ho, “Partitioning-free 3D-IC Floorplanning,” Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), pp., Hong Kong, January 2026.
16. Z. Zhuang, Z. Yang, Y. Zhao, J. Hu, B. Yu, S. K. Lim, and T.-Y. Ho, “DPO-3D: Differentiable Power Delivery Network Optimization via Flexible Modeling for Routability and IR-Drop Tradeoff in Face-to-Face 3D ICs,” Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), pp., Hong Kong, January 2026.
17. Z. Yang, Z. Zhuang, T.-Y. Ho, and S. K. Lim, “Graph Attention-Based Current Crowding Analysis at TSV Interfaces in 3D Power Delivery Networks,” Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), pp., Hong Kong, January 2026 (Best Paper Nomination).
18. *P. Xu, Y. Li, T. Chen, T.-Y. Ho, and B. Yu, “KCLNet: Electrically Equivalence-Oriented Graph Representation Learning for Analog Circuits, (AAAI), pp., Singapore, January 2026.
19. Z. Yang, S. Li, L. Jin, T.-Y. Ho, and C.-N. Liu, “IDDA-3D: Inter-Die Delay Aware Timing-Driven Placement on Face-to-Face Bonded 3D ICs,” Proceedings of ACM International Symposium on Physical Design (ISPD), pp., Bonn, Germany, March 2026.
20. L. Xiao, Q. Duan, L. Jin, J. Liu, T.-Y. Ho, F.Y. Young, and Martin Wong, “Gradient-Guided RC Weighting for Timing-Driven Global Routing,” Proceedings of ACM International Symposium on Physical Design (ISPD), pp., Bonn, Germany, March 2026.
21. Y. Ye, C.-K. Shen, X. Hu, Y. Liu, S. Yin, X. Yao, T.-Y. Ho, and B. Yu, “LongRTL: Graph-Similarity-Guided LLM-driven Long Context RTL Optimization,” Proceedings of IEEE/ACM Design, Automation and Test in Europe (DATE), pp., Verona, Italy, April 2026 (Best Paper Award).
22. Z. Wang, T. Hou, C. Wang, Z. Zhuang, T.-Y. Ho, F. Farnia, and B. Yu, “FastRW: An Efficient Random Walk Method for Steady-State Thermal Analysis,” Proceedings of IEEE/ACM Design, Automation and Test in Europe (DATE), pp., Verona, Italy, April 2026.
23. C. Wang, Z. Zhuang, K. Zhu, D. Huang, L. Costero, R. Chen, D. Atienza, and T.-Y. Ho, “ETLA-3D: Equivalent Thin Layer Aggregation based Thermal FEM for Hybrid Bonding F2F 3D ICs,” Proceedings of IEEE/ACM Design, Automation and Test in Europe (DATE), pp., Verona, Italy, April 2026.
24. P. Xu, Z. Yu, Y. Pu, X. Zhang, D. Luo, H. Geng, S. Xu, T.-Y. Ho, and B. Yu, “RATuner: Retrieval-Augmented VLSI Flow Design Parameter Tuning Framework,” Proceedings of IEEE/ACM Design, Automation and Test in Europe (DATE), pp., Verona, Italy, April 2026.
25. R. Fu, W. Xuan, S. Yin, G. Hu, C. Chen, H. Zhang, B. Yu, and T.-Y. Ho, “eLogic: A E-Graph-based Logic Rewriting Framework for Majority-Inverter Graphs,” Proceedings of IEEE/ACM Design, Automation and Test in Europe (DATE), pp., Verona, Italy, April 2026.
26. Y. Han, B. Li, R. Fu, Q. Ye, Z. Lu, J. Liu, B. Yu, T.-Y. Ho, and T. Chen, “PCB-Migrator: Automated PCB PnR Migration,” Proceedings of IEEE/ACM Design, Automation and Test in Europe (DATE), pp., Verona, Italy, April 2026.
27. Z. Di, J. Tu, Z. He, Y. Pu, J. Liu, C. Tong, T.-Y. Ho, B. Yu, and T. Chen, “Smart-PCLib: A LLM-based Multi-Agent Framework for Automated PCB Component Library Generation,” Proceedings of IEEE/ACM Design, Automation and Test in Europe (DATE), pp., Verona, Italy, April 2026 (Best Paper Nomination).
28. Q. Shen, C. Zhang, H. Xu, Z. Yu, B. Guo, Y. Zhao, B. Yu, T.-Y. Ho, and X. Huang, “HPPlacer: A High-
Precision Slack-Aware Global Placement Engine,” Proceedings of IEEE/ACM Design, Automation and Test in Europe (DATE), pp., Verona, Italy, April 2026.
29. Y. Bai, M. Fan, T.-Y. Ho, and Z. Jin, “From Forest to Tree: Prioritizing the Maximum Additional Delay in AQFP Circuit Design,” Proceedings of IEEE/ACM Design, Automation and Test in Europe (DATE), pp., Verona, Italy, April 2026.
30. Y. Huang, J. Liu, Y. She, R. Fu, T.-Y. Ho, H. Yen, and R. Cheung, “Chariot: Compiler-Aware Heterogeneous Graph Representation Learning for Automated HLS Optimization,” Proceedings of IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp., Atlanta, GA, May 2026.
31. R. Zhang, R. Fu, S. Ren, W. Li, D. Wang, F. Wang, X. Ye, T.-Y. Ho, and J. Huang, ”THLR: A Top-down Hierarchical Logic Rewrite Framework for Xor-Majority-Inverter Graphs,” Proceedings of ACM Great Lake Symposium on VLSI (GLSVLSI), pp., Finger Lakes, NY, June 2026.
32. *Y. Han, B. Li, M. Zhao, R. Fu, Q. Ye, T. Chen, B. Yu, and T.-Y. Ho, “ModuPlace: LLM-Assisted Modular PCB Placement via Preference-Optimized Constraint Graph Generation,” Proceedings of ACM/IEEE Design Automation Conference (DAC), pp., Long Beach, CA, July 2026.
33. *S. Liang, S. Li, L. Jin, Y. Pu, Y. Zhang, Z. Zhuang, K.-Y. Chao, U. Schlichtmann, and T.-Y. Ho, “BLADE: Bi-Level Bayesian Optimization for Metal-Density-Constrained Multi-Layer Package Power/Ground Plane Synthesis” Proceedings of ACM/IEEE Design Automation Conference (DAC), pp., Long Beach, CA, July 2026.
34. *L. Jin, H. Xu, S. Liang, Z. Zhuang, Z. Hu, Z. WANG, B. Yu, R. Chen, and T.-Y. Ho, “BSPDN-Elite: A Comprehensive Framework for Optimizing Timing, Power and Routing Resources in BSPDN Designs,” Proceedings of ACM/IEEE Design Automation Conference (DAC), pp., Long Beach, CA, July 2026.
35. *S. Li, L. Jin, S. Liang, Z. Zhuang, R. Chen, B. Yu, and T.-Y. Ho, “FlexiCTS: CPPR-Aware 3D Clock Tree Synthesis for Face-to-Face Bonded ICs,” Proceedings of ACM/IEEE Design Automation Conference (DAC), pp., Long Beach, CA, July 2026.
36. *R. Fu, Y. Liu, Q. Xu, and T.-Y. Ho, “MappingEvolve: LLM-Driven Code Evolution for Technology Mapping,” Proceedings of ACM/IEEE Design Automation Conference (DAC), pp., Long Beach, CA, July 2026.
37. *P. Xu, M. Wang, Y. Li, Y. Ye, T. Chen, T.-Y. Ho, and B. Yu “DiffSP: Differentiable Sequence Pair-based Analog Placement,” Proceedings of ACM/IEEE Design Automation Conference (DAC), pp., Long Beach, CA, July 2026.
38. *H. Xu, Z. Yang, Z. Zhuang, L. Jin, B. Yu, S. K. Lim, and T.-Y. Ho, “RTL-3D: Timing-aware Tier Partitioning for 3D ICs Using Pre-synthesis Timing Analysis,” Proceedings of ACM/IEEE Design Automation Conference (DAC), pp., Long Beach, CA, July 2026.
39. *H. Xu, Z. Zhuang, L. Jin, Z. Yang, C. Wu, L. He, S. K. Lim, and T.-Y. Ho, “Mixed-structure Double-sided Redistribution Layer Routing for Glass Interposer-based 5.5D ICs,” Proceedings of ACM/IEEE Design Automation Conference (DAC), pp., Long Beach, CA, July 2026.
40. *X. Ren, Y. Huang, Z. Zhang, Y. Zhu, T.-Y. Ho, A. Barbalace, and Z. Liang, “Photonic Quantum Computing on Spin Memory Architecture with Tree-Encoded Fusion,” Proceedings of IEEE International Symposium on Computer Architecture (ISCA), pp., Raleigh, NC, July 2026.
41. *C. Xiong, Z. Wang, R. Zhu, T.-Y. Ho, P.-Y. Chen, J. Xiong, and H. Tang, “Hey, That’s My Data! Token-Only Dataset Inference in Large Language Models,” Findings of the Association for Computational Linguistics: ACL 2025 (Findings of ACL), pp., San Diego, CA, July 2026.
42. *Z. Li, P.-Y. Chen, and T.-Y. Ho, “GRE Score: Generative Risk Evaluation for Large Language Models,” Findings of the Association for Computational Linguistics: ACL 2025 (Findings of ACL), pp., San Diego, CA, July 2026.
43. *L. Hsiung, T. Pang, Y.-C. Tang, L. Song, T.-Y. Ho, P.-Y. Chen, and Y. Yang “Why LLM Safety Guardrails Collapse After Fine-tuning: A Similarity Analysis Between Alignment and Fine-tuning Datasets,” Proceedings of the Annual Meeting of the Association for Computational Linguistics (ACL), pp., San Diego, CA, July 2026.
44. *Y. Han, R. Fu, Y. Liu, S. Ren, S. Dong, Y. Wang, T. Chen, B. Yu, and T.-Y. Ho, ”Expert-level Leaf Cell Layout Generation via Preference-Optimized LLM,” Proceedings of International Conference on Machine Learning (ICML), pp., Seoul, Korea, July 2026.
45. *C. Wang, P. Zuo, Z. Chen, Q. Zhou, T.-Y. Ho, and M.-C. Yang ”TileSparse: Arithmetic-Intensity-Aware Sparse Attention for Compute-Bound LLM Decoding,” Proceedings of International Conference on Machine Learning (ICML), pp., Seoul, Korea, July 2026.
46. *Y. Liu, M. Wang, P. XU, R. Fu, B. Yu, and T.-Y. Ho, ”AnalogVerifier: A Neuro-Symbolic Framework for Analog Circuit Verification,” Proceedings of International Conference on Machine Learning (ICML), pp., Seoul, Korea, July 2026.
· Tiến sĩ Kỹ thuật Điện, Đại học Quốc gia Đài Loan (2005)
· Thạc sĩ Khoa học Máy tính, Đại học Giao thông Quốc gia Đài Loan (2001)
· Cử nhân Khoa học Máy tính, Đại học Tunghai, Đài Loan (1999)
• 2023 IEEE Fellow
• 2021 Global STEM Scholar, Hong Kong
• 2020 Prolific Author Award, ACM/IEEE ASP-DAC
• 2019 ACM Distinguished Member
• 2019 JSPS Invitation Fellowship, Japan Society for the Promotion of Science, Japan
• 2017 Faculty Research Award, National Tsing Hua University, Taiwan
• 2017 International Visiting Research Scholar, The Peter Wall Institute for Advanced Studies, The University of British Columbia, Canada
• 2017 Observational Research Award, The Pan Wen Yuan Foundation, Taiwan
• 2016 IEEE CAS Distinguished Lecturer
• 2014 ACM Distinguished Speaker
• 2014 Hans Fischer Fellowship, Institute for Advanced Study, Technical University of Munich, Germany
• 2014 JSPS Invitation Fellowship, Japan Society for the Promotion of Science, Japan
• 2014 Award for Junior Research Investigators, Academia Sinica, Taiwan
• 2013 NCKU K. T. Li Research Award, Delta Research Foundation, Taiwan
• 2013 IEEE Distinguished Visitor (Asia and Pacific), IEEE Computer Society (2013~2015)
• 2012 Dr. Ta-You Wu Memorial Award, National Science Council, Taiwan
• 2012 Distinguished Young Scholar Award, Taiwan IC Design Society
• 2012 Excellent Young Researcher Project Award, National Science Council, Taiwan
• 2012 K. T. Li Young Scholar Research Award, ACM Taipei Section
• 2011 Best GOLD Member Award, IEEE Tainan Section
• 2011 Excellent Teaching Award, National Cheng Kung University
• 2011 Hildegard Maier Research Fellowship, Alexander von Humboldt Foundation
• 2011 JSPS Invitation Fellowship, Japan Society for the Promotion of Science, Japan
